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ASIC Engineering Technical Leader (Design)

Cisco Meraki – Leader, Technical Marketing Engineering – Network Platform

ASIC Design Verification Engineer | UVM | Exp- 8+ Years

ASIC Design Engineer – Design & Timing Constraints

Production Engineering Technical Lead | Kubernetes, Microservices (Development in GO/Python), CI/CD | 12-16 years

Lead Machine Learning Engineer, Ops (Lead, MLE Ops) – Meraki

Lead Machine Learning Engineer (MLE) Network Platform/Assurance- Meraki

Software Development Engineer in Test, San Jose, CA

FPGA Verification Engineer || Verilog/System Verilog/UVM Methodologies || Experience 8+ years

Senior Product Designer

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